Design for Testability That Reduces Linearity Testing Time of SAR ADCs
نویسندگان
چکیده
This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable. key words: SAR ADC, testing, DC linearity, design for testability, built-in self-test
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عنوان ژورنال:
- IEICE Transactions
دوره 94-C شماره
صفحات -
تاریخ انتشار 2011